1. Field of the Invention
The invention relates to a pattern of voids in an integrated circuit and to a method for producing a pattern of voids in an integrated circuit.
Integrated circuit arrangements are being produced with ever higher packing densities. This means that interconnects in metallization levels are at an ever increased shorter distance from one another. This causes capacitances which are formed between the interconnects and lead to high signal propagation times, high power loss and crosstalk. Hitherto, to provide isolation between the interconnects primarily SiO2 has been used as a dielectric whose relative permittivity is εr=3.9.
2. Description of the Related Prior Art
There are a number of known methods for reducing the relatively permittivity εr and therefore for lowering the capacitance between interconnects within an interconnect level, for example from [1] or [2].
According to the cited prior art, voids are produced between the interconnects within an interconnect level. The isolating dielectric, which determines the capacitance between the interconnects, therefore has a relative permittivity εr which is virtually equal to unity. The interconnects themselves are enclosed at the top and bottom by solid SiO2 layers for isolation purposes.